Please use this identifier to cite or link to this item: https://scholar.dlu.edu.vn/handle/123456789/3305
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dc.contributor.authorJi-Ting Liangen_US
dc.contributor.authorChun-Hsing Shihen_US
dc.contributor.authorYan-Xiang Luoen_US
dc.contributor.authorMing-Kun Huangen_US
dc.contributor.authorNguyễn, Đăng Chiếnen_US
dc.contributor.authorRuei-Kai Shiaen_US
dc.contributor.authorSau-Mou Wuen_US
dc.contributor.authorChenhsin Lienen_US
dc.contributor.authorWen-Fa Wuen_US
dc.date.accessioned2024-03-02T09:51:07Z-
dc.date.available2024-03-02T09:51:07Z-
dc.date.issued2011-
dc.identifier.urihttps://scholar.dlu.edu.vn/handle/123456789/3305-
dc.description.abstractThe edge thinning of tunnel oxide is numerically found to increase the Fowler-Nordheim (FN) tunneling gate current in NAND-type Flash cells during programming and erasing operations. This work explores the effect of edge thinning profile in tunnel-oxide on FN tunneling current, and examines the impact of symmetrical and asymmetric geometry on the FN tunneling current in NAND-type Flash cells.en_US
dc.language.isoenen_US
dc.titleEffects of Edge Thinning on Fowler-Nordheim Tunneling Current of NAND-Type Flash Memory Cellsen_US
dc.typeConference paperen_US
dc.relation.conferenceSymposium on Nano Device Technology (SNDT)en_US
dc.relation.references[1] International Technology Roadmap for Semiconductor, 2007 edition. [2] Y. Taur and Tak H. Ning, Fundamentals of modern VLSI devices, Cambridge University Press, 1998. [3] K. Prall, “Scaling non-volatile memory below 30nm,” in IEEE NVSMW, 2007, pp. 5-9. [4] H. Yang, H. Kim, S.-I. Park, J. Kim, S.-H. Lee, J.-K. Choi, D. Hwang, C. Kim, M. Park, K.-H. Lee, Y.-K. Park, J. K. Shin, and J.-T. Kong, “Reliability issues and models of sub-90nm NAND Flash memory cells,” in IEEE Int. Conf. on Solid-State and Integrated-Circuit Technology, 2006, pp. 760-762. [5] B. Kim, W.-H. Kwon, C.-K. Baek, Y. Son, C.-K. Park, K. Kim, and D. M. Kim, “Edge profile effect of tunnel oxide on erase threshold-voltage distributions in Flash memory cells,” IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 3012-3019, Dec. 2006. [6] J. Lee, J. Kim, W. Lee, S. Lee, H. Lim, J. Lee, S. Nam, H. Lee and C. Song, “Effect of STI shape and tunneling oxide thinning on cell Vth variation in the flash memory” in Proc. IEEE IRPS, 2005, pp. 670-671. [7] M. Park, K. Suh, K. Kim, S.-H. Hur, K. Kim, and W.-S. Lee, “The effect of trapped charge distributions on data retention characteristics of NAND Flash memory cells,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 750-752, Aug. 2007. [8] H. Watanabe, K. Shimizu, Y. Takeuchi, and S. Aritome, “Corner-rounded shallow trench isolation technology to reduce the stress-induced tunnel oxide leakage current for highly reliable flash memories,” in IEDM Tech. Dig., 1996, pp. 833-836. [9] C.-Y. Ho, C.-H. Shih, ”Edge encroachments and suppressions of tunnel oxide in Flash memory cells,” IEEE Electron Devices Lett., vol. 29, pp. 1159-1162, Oct. 2008. [10] M. Park, C.-S. Lee, S.-H. Hur, K. Kim, and W.-S. Lee, “The effect of field oxide recess on cell VTHdistribution of NAND Flash cell arrays,” IEEE Electron Devices Lett., vol. 29, pp. 1050-1052, Sep. 2008. [11] Synopsys MEDICI User’s Manual, Synopsys Inc., Mountain View, CA, 2006.en_US
dc.type.reportBài báo đăng trên KYHT trong và ngoài nước (không có ISBN)en_US
dc.publisher.placeTaiwan (China)en_US
item.fulltextWith Fulltext-
item.grantfulltextrestricted-
item.languageiso639-1other-
crisitem.author.deptFaculty of Physics and Nuclear Engineering-
crisitem.author.orcidhttps://orcid.org/0000-0003-2329-5860-
crisitem.author.parentorgDalat University-
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