1. Hệ thống quản lý thông tin nghiên cứu (DLU Research Information Management System)
  2. Faculty of Physics and Nuclear Engineering
  3. Tạp chí (Khoa Vật lý và Kỹ thuật hạt nhân)
Please use this identifier to cite or link to this item: https://scholar.dlu.edu.vn/handle/123456789/3298
DC FieldValueLanguage
dc.contributor.authorChun-Hsing Shihen_US
dc.contributor.authorWei Changen_US
dc.contributor.authorYan-Xiang Luoen_US
dc.contributor.authorJi-Ting Liangen_US
dc.contributor.authorMing-Kun Huangen_US
dc.contributor.authorNguyễn, Đăng Chiếnen_US
dc.contributor.authorRuei-Kai Shiaen_US
dc.contributor.authorJr-Jie Tsaien_US
dc.contributor.authorWen-Fa Wuen_US
dc.contributor.authorChenhsin Lienen_US
dc.date.accessioned2024-03-01T07:55:10Z-
dc.date.available2024-03-01T07:55:10Z-
dc.date.issued2011-
dc.identifier.urihttps://scholar.dlu.edu.vn/handle/123456789/3298-
dc.description.abstractA new Schottky barrier (SB) nonvolatile nanowire memory is reported experimentally with efficient low-voltage programming and erasing. By applying an SB source/drain to enhance the electrical field in the silicon gate-all-around nanowire, the nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory can operate at gate voltages of 5 to 7 V for programming and -7 to -9 V for erasing through Fowler-Nordheim tunneling. The larger the gate voltage is, the faster the programming/erasing speed and the wider the threshold-voltage shift are attained. Importantly, the SB nanowire SONOS cells exhibit superior 100-K cycling endurance and high-temperature retention without any damages from metallic silicidation process or field-enhanced tunneling.en_US
dc.language.isoenen_US
dc.publisherIEEE Publishingen_US
dc.relation.ispartofIEEE Electron Device Lettersen_US
dc.subjectGate-all-around nanowireen_US
dc.subjectSchottky barrier (SB)en_US
dc.subjectSilicon–oxide-nitride-oxide-silicon (SONOS) memoryen_US
dc.titleSchottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltagesen_US
dc.typeJournal articleen_US
dc.identifier.doi10.1109/LED.2011.2164510-
dc.relation.issn0741-3106en_US
dc.description.volume32en_US
dc.description.issue11en_US
dc.relation.references[1] S. D. Suk, K. H. Yeo, K. H. Cho, M. Li, Y. Y. Yeoh, K.-H. Hong, S.-H. Kim, Y.-H. Koh, S. Jung, W. J. Jang, D.-W. Kim, D. Park, and B.-I. Ryu, “Gate-all-around twin silicon nanowire SONOS memory,” in VLSI Symp. Tech. Dig., 2007, pp. 142–143. [2] J. Fu, N. Singh, K. D. Buddharaju, S. H. G. Teo, C. Shen, Y. Jiang, C. X. Zhu, M. B. Yu, G. Q. Lo, N. Balasubramanian, D. L. Kwong, E. Gnani, and G. Baccarani, “Si-nanowire based gate-all-around nonvolatile SONOS memory cell,”IEEE Electron Device Lett., vol. 29, no. 5, pp. 518–521, May 2008. [3] K.H.Yeo,K.H.Cho,M.Li,S.D.Suk,Y.-Y.Yeoh,M.-S.Kim, H. Bae, J.-M. Lee, S.-K. Sung, J. Seo, B. Park, D.-W. Kim, D. Park, and W.-S. Lee, “Gate-all-around single silicon nanowire MOSFET with 7 nm width for SONOSNANDFlash memory,” inVLSI Symp. Tech. Dig., 2008, pp. 138–139. [4] J. Fu, Y. Jiang, N. Singh, C. X. Zhu, G. Q. Lo, and D. L. Kwong, “Polycrystalline Si nanowire SONOS nonvolatile memory cell fabricated on a gate-all-around (GAA) channel architecture,”IEEE Electron Device Lett., vol. 30, no. 3, pp. 246–249, Mar. 2009. [5] D.-I. Moon, S.-J. Choi, C.-J. Kim, J.-Y. Kim, J.-S. Lee, J.-S. Oh, G.-S. Lee, Y.-C. Park, D.-W. Hong, D.-W. Lee, Y.-S. Kim, J.-W. Kim, J.-W. Han, and Y.-K. Choi, “Ultimately scaled 20 nm unified-RAM,” in IEDM Tech. Dig., 2010, pp. 284–287. [6] T.-C. Lia, S.-K. Chen, M. H. Yu, C.-Y. Wu, T.-K. Kang, F.-T. Chien, Y.-T. Liu, C.-M. Lin, and H.-C. Cheng, “A novel LTPS-TFT-based chargetrapping memory device with field-enhanced nanowire structure,” in IEDM Tech. Dig., 2009, pp. 207–210. [7] P.-C. Huang, L.-A. Chen, and J.-T. Sheu, “Electric-field enhancement of a gate-all-around nanowire thin-film transistor memory,”IEEE Electron Device Lett., vol. 31, no. 3, pp. 216–218, Mar. 2010. [8] M. Chen, H. Y. Yu, N. Singh, Y. Sun, N. S. Shen, X. Yuan, G.-Q. Lo, and D.-L. Kwong, “Vertical-Si-nanowire SONOS memory for ultrahighdensity application,”IEEE Electron Device Lett., vol. 30, no. 8, pp. 879–881, Aug. 2009. [9] C.-H. Shih and J.-T. Liang, “Nonvolatile Schottky barrier multibit cell with source-side injected programming and reverse drain-side hole erasing,” IEEE Trans. Electron Devices, vol. 57, no. 8, pp. 1774–1780, Aug. 2010. [10] K. Uchida, K. Matsuzawa, J. Koga, S. Takagi, and A. Toriumi, “Enhancement of hot-electron generation rate in Schottky source metal–oxide–semiconductor field-effect transistors,”Appl. Phys. Lett., vol. 76, no. 26, pp. 3992–3994, Jun. 2000. [11] C.-H. Shih, S.-P. Yeh, J.-T. Liang, and Y.-X. Luo, “Source-side injection Schottky barrier Flash memory cells,”Semicond. Sci. Technol., vol. 24, no. 2, p. 025 013, Feb. 2009. [12] S.-J. Choi, J.-W. Han, S. Kim, D.-H. Kim, M.-G. Jang, J.-H. Yang, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, “High speed Flash memory and 1T-DRAM on dopant segregated Schottky barrier (DSSB) FinFET SONOS device for multi-functional SoC applications,” in IEDM Tech. Dig., 2008, pp. 223–226. [13] S.-J. Choi, J.-W. Han, S. Kim, M.-G. Jang, J. S. Kim, K. H. Kim, G. S. Lee, J. S. Oh, M. H. Song, Y. C. Park, J. W. Kim, and Y.-K. Choi, “Enhancement of program speed in dopant-segregated Schottky-barrier (DSSB) FinFET SONOS forNAND-type Flash memory,”IEEE Electron Device Lett., vol. 30, no. 1, pp. 78–81, Jan. 2009. [14] H. Iwai, T. Ohguro, and S.-I. Ohmi, “NiSi salicide technology for scaled CMOS,”Microelectron. Eng., vol. 60, no. 1/2, pp. 157–169, Jan. 2002. [15] C.-F. Huang and B.-Y. Tsui, “Short-channel metal-gate TFTs with modified Schottky-barrier source/drain,” IEEE Electron Device Lett., vol. 27, no. 1, pp. 43–45, Jan. 2006.en_US
dc.description.pages1477-1479en_US
dc.type.reportBài báo đăng trên tạp chí thuộc ISI, bao gồm book chapteren_US
dc.publisher.placeUSAen_US
item.fulltextWith Fulltext-
item.grantfulltextrestricted-
item.languageiso639-1other-
crisitem.author.deptFaculty of Physics and Nuclear Engineering-
crisitem.author.orcidhttps://orcid.org/0000-0003-2329-5860-
crisitem.author.parentorgDalat University-
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