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https://scholar.dlu.edu.vn/handle/123456789/3298| Title: | Schottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltages | Authors: | Chun-Hsing Shih Wei Chang Yan-Xiang Luo Ji-Ting Liang Ming-Kun Huang Nguyễn, Đăng Chiến Ruei-Kai Shia Jr-Jie Tsai Wen-Fa Wu Chenhsin Lien |
Keywords: | Gate-all-around nanowire;Schottky barrier (SB);Silicon–oxide-nitride-oxide-silicon (SONOS) memory | Issue Date: | 2011 | Place of publication: | USA | Publisher: | IEEE Publishing | Journal: | IEEE Electron Device Letters | Volume: | 32 | Issue: | 11 | Pages: | 1477-1479 | Abstract: | A new Schottky barrier (SB) nonvolatile nanowire memory is reported experimentally with efficient low-voltage programming and erasing. By applying an SB source/drain to enhance the electrical field in the silicon gate-all-around nanowire, the nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory can operate at gate voltages of 5 to 7 V for programming and -7 to -9 V for erasing through Fowler-Nordheim tunneling. The larger the gate voltage is, the faster the programming/erasing speed and the wider the threshold-voltage shift are attained. Importantly, the SB nanowire SONOS cells exhibit superior 100-K cycling endurance and high-temperature retention without any damages from metallic silicidation process or field-enhanced tunneling. |
URI: | https://scholar.dlu.edu.vn/handle/123456789/3298 | DOI: | 10.1109/LED.2011.2164510 | Type: | Bài báo đăng trên tạp chí thuộc ISI, bao gồm book chapter |
| Appears in Collections: | Tạp chí (Khoa Vật lý và Kỹ thuật hạt nhân) |
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| 04 EDL11_Schottky barrier silicon nanowire SONOS memory with ultralow programming and erasing voltages.PDF | 502.61 kB | Adobe PDF |
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